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74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs
May 1998
74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVQ125 contains four independent non-inverting buffers with 3-STATE outputs.
Features
n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75
Ordering Code:
Order Number 74LVQ125SC 74LVQ125SJ Package Number M14A M14D Package Description 14-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC 14-Lead Small Outline Package, SOIC EIAJ
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Assignment for SOIC JEDEC and EIAJ
DS011349-1
Pin Descriptions
Pin Names An, Bn On Description Inputs Outputs
DS011349-2
Truth Table
Inputs An L L H Bn L H X Output On L H Z
H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial
(c) 1998 Fairchild Semiconductor Corporation
DS011349
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Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to to VCC + 0.5V
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 3.0V 2.0V to 3.6V 0V to VCC 0V to VCC -40C to +85C
125 mV/ns
50 mA 200 mA -65C to +150C 100 mA
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteritics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Parameter VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.6 0.002 TA = +25C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 1.5 1.5 2.99 2.0 0.8 2.9 2.58 0.1 0.36 TA = -40C to +85 C Guaranteed Limits 2.0 0.8 2.9 2.48 0.1 0.44 V V V V V V A VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH (Note 3) IOH = -12 mA VOL Maximum Low Level Output Voltage IOUT = 50 A VIN = VIL or VIH (Note 3) IOL = 12 mA IIN IOZ Maximum Input Leakage Current Maximum 3-STATE Leakage Current VI = VCC, GND VI (OE) = VIL, VIH 3.6 3.6 3.6 3.6 3.3 3.3 3.3 3.3 0.6 -0.6 1.7 1.5 4.0 1.0 -1.0 2.0 0.8 Units Conditions
0.1
1.0
0.25
2.5
36 -25 40.0
A mA mA A V V V V
VI = VCC, GND VO = VCC, GND VOLD = 0.8V Min (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND (Notes 6, 7) (Notes 6, 7) (Notes 6, 8) (Notes 6, 8)
IOLD IOHD ICC VOLP VOLV VIHD VILD
Minimum Dynamic (Note 4) Output Current Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75 for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
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2
AC Electrical Characteristics
Symbol Parameter VCC (V) Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL, tOSLH Propagation Delay Data to Output Propagation Delay Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time Output to Output Skew (Note 9) Data to Output 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 TA = +25C CL = 50 pF Typ 7.8 6.5 7.8 6.5 7.2 6.0 9.0 7.5 9.0 7.5 9.0 7.5 1.0 1.0 Max 12.7 9.0 12.7 9.0 14.8 10.5 14.0 10.0 14.0 10.0 14.8 10.5 1.5 1.5 TA = -40C to +85C CL = 50 pF Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 14.0 10.0 14.0 10.0 16.0 11.0 16.0 11.0 15.0 10.5 16.5 11.5 1.5 1.5 ns ns ns ns ns ns ns Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol CIN CPD (Note 10) Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 34 Units pF pF Conditions VCC = Open VCC = 3.3V
Note 10: CPD is measured at 10 MHz.
3
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4
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead (0.150" Wide) Small Outline Integrated Circuit Package Number M14A
14-Lead Small Outline Package EIAJ Package Number M14D
5
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74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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